PCAL6416AEX1数据手册恩XP中文资料规格书

描述 Description

The PCAL6416A is a 16-bit general purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I2C-bus interface.
NXP® I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. The PCAL6416A has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/O voltages is required. Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCAL6416A: VDD(I²C-bus) and VDD(P). VDD(I²C-bus)provides the supply voltage for the interface at the master side (for example, amicrocontroller) and the VDD(P) provides the supply for core circuits and Port P. Thebi-directional voltage level translation in the PCAL6416A is provided through VDD(I²C-bus).VDD(I²C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicatesthe VDD level of the I²C-bus to the PCAL6416A, while the voltage level on Port P of thePCAL6416A is determined by the VDD(P).
The PCAL6416A contains the PCA6416A register set of four pairs of 8-bit Configuration,Input, Output, and Polarity Inversion registers and additionally, the PCAL6416A hasAgile I/O, which are additional features specifically designed to enhance the I/O. Theseadditional features are programmable output drive strength, latchable inputs,programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register,programmable open-drain or push-pull outputs. The PCAL6416A is a pin-to-pinreplacement to the PCA6416A, however, the PCAL6416A powers up with all I/O interruptsmasked. This mask default allows for a board bring-up free of spurious interrupts atpower-up.
At power-on, the I/Os are configured as inputs. However, the system master can enablethe I/Os as either inputs or outputs by writing to the I/O configuration bits. The data foreach input or output is kept in the corresponding input or output register. The polarity ofthe Input Port register can be inverted with the Polarity Inversion register, saving externallogic gates. Programmable pull-up and pull-down resistors eliminate the need for discretecomponents.
The system master can reset the PCAL6416A in the event of a time-out or other improperoperation by asserting a LOW in the RESET input. The power-on reset puts the registersin their default state and initializes the I²C-bus/SMBus state machine. The RESET pincauses the same reset/initialization to occur without depowering the part.
The PCAL6416A open-drain interrupt (INT) output is activated when any input state differsfrom its corresponding Input Port register state and is used to indicate to the systemmaster that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interruptsignal on this line, the remote I/O can inform the microcontroller if there is incoming dataon its ports without having to communicate via the I²C-bus. Thus, the PCAL6416A canremain a simple slave device. The input latch feature holds or latches the input pin stateand keeps the logic values that created the interrupt until the master can service theinterrupt. This minimizes the host’s interrupt service response for fast moving inputs.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs whileconsuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C-bus addressand allow up to two devices to share the same I²C-bus or SMBus.

特性 Features

• I²C-bus to parallel port expander
• Operating power supply voltage range of 1.65 V to 5.5 V
• Allows bidirectional voltage-level translation and GPIO expansion between:
• 1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
• 2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
• 3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
• 5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
• Low standby current consumption:
• 1.5 μA typical at 5 V VDD
• 1.0 μA typical at 3.3 V VDD
• Schmitt trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs
• Vhys = 0.18 V (typical) at 1.8 V
• Vhys = 0.25 V (typical) at 2.5 V
• Vhys = 0.33 V (typical) at 3.3 V
• Vhys = 0.5 V (typical) at 5 V
• 5 V tolerant I/O ports
• Active LOW reset input (RESET)
• Open-drain active LOW interrupt output (INT)
• 400 kHz Fast-mode I²C-bus
• Internal power-on reset
• Power-up with all channels configured as inputs
• No glitch on power-up
• Noise filter on SCL/SDA inputs
• Latched outputs with 25 mA drive maximum capability for directly driving LEDs
• Latch-up performance exceeds 100 mA per JESD 78, Class II
• ESD protection exceeds JESD 22
• 2000 V Human-Body Model (A114-A)
• 1000 V Charged-Device Model (C101)
• Packages offered: TSSOP24, HWQFN24, UFBGA24, VFBGA24, XFBGA24, X2QFN24
Agile I/O features
• Software backward compatible with PCA6416A with interrupts disabled at power-up
• Pin-to-pin drop-in replacement with PCA6416A
• Output port configuration: bank selectable push-pull or open-drain output stages
• Interrupt status: read-only register identifies the source of an interrupt
• Bit-wise I/O programming features:
• Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance applications
• Input latch: Input Port register values changes are kept until the Input Port registeris read
• Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable
• Pull-up/pull-down selection: 100 kΩ pull-up/pull-down resistor selection
• Interrupt mask: mask prevents the generation of the interrupt when input changesstate to prevent spurious interrupts