PCA9846BS数据手册恩XP中文资料规格书

描述 Description

The PCA9846 is an ultra-low voltage, quad bidirectional translating switch controlled via the
\t\t\t\tI²C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or
\t\t\tchannels. Any or all SCx/SDx channels can be selected, determined by the programmable
\t\t\tcontrol register. This feature allows multiple devices with the same I²C-bus
\t\t\taddress to reside on the same bus. The switch device can also separate a heavily loaded
\t\t\t\tI²C-bus into separate bus segments, eliminating the need for a bus
\t\t\tbuffer.

An active LOW reset input allows the PCA9846 to recover from a situation where one of the
\t\t\tdownstream I²C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus state machine
\t\t\tand deselects all the channels, as does the internal Power-On Reset (POR) function.

The pass gates of the switches are constructed such that the VDD1 pin is used
\t\t\tto limit the maximum high voltage which is passed by the PCA9846. This allows the use of
\t\t\tdifferent bus voltages on each channel, so that 0.8 V, 1.8 V, 2.5 V or 3.3 V parts can
\t\t\tcommunicate without any additional protection. External pull-up resistors pull the bus
\t\t\tup to the desired voltage level for each channel. All I/O pins are 3.6 V tolerant.

特性 Features

\t\t\t\t\tUltra-low voltage operation, down to 0.8 V to interface with next-generation CPUs
\t\t\t\t


\t\t\t\t1-of-4 bidirectional translating switch
\t\t\t


\t\t\t\tFm+ I²C-bus interface logic; compatible with SMBus standards
\t\t\t


\t\t\t\t2 address pins allowing up to 16 devices on the I²C-bus
\t\t\t


\t\t\t\tChannel selection via I²C-bus
\t\t\t


\t\t\t\tPower-up with all switch channels deselected
\t\t\t


\t\t\t\tLow Ron switches
\t\t\t


\t\t\t\tAllows voltage level translation between 0.8 V, 1.8 V, 2.5 V and 3.3 V buses
\t\t\t


\t\t\t\tReset via I²C-bus software command
\t\t\t


\t\t\t\tI²C Device ID function
\t\t\t


\t\t\t\tNo glitch on power-up
\t\t\t


\t\t\t\tSupports hot insertion since all channels are de-selected at power-on
\t\t\t


\t\t\t\tLow standby current
\t\t\t


\t\t\t\t3.6 V tolerant inputs
\t\t\t


\t\t\t\t0 Hz to 1 MHz clock frequency
\t\t\t


\t\t\t\tESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM per
\t\t\t\t\tJESD22-C101
\t\t\t


\t\t\t\tLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
\t\t\t


\t\t\t\tTwo packages offered: TSSOP16 and HVQFN16
\t\t\t