零件型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
---|---|---|---|---|
PCA9574BS | 8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt; 400 kHz I²C-bus serial interface\nCompliant with I²C-bus Standard-mode (100 kHz)\nSeparate supply rails for core logic and I/O bank provides voltage level shifting\n1.1 V to 3.6 V operation with level shifting feature\nVery low standby current: < 1 µA\n8 configurable I/O pins that default to inputs at power-up\nOutputs: Totem pole: 1 mA source and 3 mA sink\nIndependently programmable 100 kΩ pull-up or pull-down for each I/O pin\nOpen-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs\nInputs: Programmable bus hold provides valid logic level when inputs are not actively driven\nProgrammable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up\nPolarity inversion register allows inversion of the polarity of the I/O pins when read\nActive LOW reset (RESET) input pin resets device to power-up default state\nGPIO All Call address allows programming of more than one device at the same time with the same parameters\n2 programmable slave addresses using 1 address pin\n-40 °C to +85 °C operation\nESD protection exceeds 7000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101\nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA\nPackages offered: TSSOP16 and HVQFN16\n; The PCA9574 is a CMOS device that provides 8 bits of General Purpose parallelInput/Output (GPIO) expansion in low voltage processor and handheld battery poweredmobile applications and was developed to enhance the NXP family of I²C-bus I/Oexpanders. The improvements include lower supply current, lower operating voltage of1.1 V to 3.6 V, dual and separate supply rails to allow voltage level translation anywherebetween 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of theeight I/O ports can be configured as an input or output independent of each other anddefault on start-up to inputs. I/O expanders provide a simple solution when additional I/Osare needed while keeping interconnections to a minimum; for example in battery poweredmobile applications and clamshell devices for interfacing to sensors, push buttons,keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection ofa processor running at one voltage level to I/O devices operating at a different (usuallyhigher) voltage level. PCA9574 has built-in level shifting feature that makes these devicesextremely flexible in mixed signal environments where communication betweenincompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as1.1 V while the I/O bank can operate in the range 1.1 V to 3.6 V. Bus-hold withprogrammable on-chip pull-up or pull-down feature for I/Os is also provided.\nThe system master can enable the I/Os as either inputs or outputs by writing to the I/Oconfiguration register bits. The data for each input or output is kept in the correspondingInput or Output register. The polarity of the read register can be inverted with the Polarityinversion register (active HIGH or active LOW operation). Either a bus-hold function orpull-up/pull-down feature can be selected by programming corresponding registers. Thebus-hold provides a valid logic level when the I/O bus is not actively driven. Whenbus-hold feature is not selected, the I/O ports can be configured to have pull-up orpull-down by programming the pull-up/pull-down configuration register.\nAn open-drain interrupt output pin (INT) allows monitoring of the input pins and is assertedeach time a change occurs on an input port unless that port is masked(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9574sat the same time even if they have different individual I²C-bus addresses. This allowsoptimal code programming when more than one device needs to be programmed with thesame instruction or if all outputs need to be turned on or off at the same time. The internalPower-On Reset (POR) or hardware reset pin (RESET) initializes the eight I/Os as inputs,sets the registers to their default values and initializes the device state machine. The I/Obank is held in its default state when the logic supply (VDD) is off.\nOne address select pin allows up to two PCA9574 devices to be connected with twodifferent addresses on the same I²C-bus.\nThe PCA9574 is available in TSSOP16 and HVQFN16 packages and isspecified over the −40 °C to +85 °C industrial temperature range.\n | NXPNXP Semiconductors 恩智浦恩智浦半导体公司 | NXP | |
Electronic,2C#18SolBC,PVCIns,OS,RedPVCJkt,FPLR ProductDescription Electronic,2Conductor18AWG(Solid)BareCopper,PVCInsulation,OverallBeldfoil®Shield,RedPVCOuterJacket,FPLR | BELDENBelden Inc. 百通电缆设计科技有限公司 | BELDEN | ||
Ethernet/GigabitEthernetClockGenerator | ADAnalog Devices 亚德诺亚德诺半导体技术有限公司 | AD | ||
Ethernet/GigabitEthernetClockGenerator | ADAnalog Devices 亚德诺亚德诺半导体技术有限公司 | AD | ||
HNTeeAdapterFemale-Female-Female | PASTERNACK Pasternack Enterprises, Inc. | PASTERNACK |
详细参数
- 型号:
PCA9574BS
- 功能描述:
转换 - 电压电平 8-BIT I2C-BUS/SMBUS
- RoHS:
否
- 制造商:
Micrel
- 类型:
CML/LVDS/LVPECL to LVCMOS/LVTTL
- 传播延迟时间:
1.9 ns
- 电源电流:
14 mA
- 电源电压-最大:
3.6 V
- 电源电压-最小:
3 V
- 最大工作温度:
+ 85 C
- 安装风格:
SMD/SMT
- 封装/箱体:
MLF-8
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
恩XP |
24+ |
QFN16 |
3524 |
原装正品,现货库存,1小时内发货 |
询价 | ||
恩XP |
25+ |
QFN16 |
32360 |
NXP/恩智浦全新特价PCA9574BS即刻询购立享优惠#长期有货 |
询价 | ||
原厂原装 |
ROHS全新原装公司 |
QFN |
10289 |
原装现货在线咨询样品※技术支持专业电子元器件授权 |
询价 | ||
恩XP |
22+ |
QFN16 |
9500 |
原装正品 |
询价 | ||
恩XP |
24+ |
N/A |
7948 |
原厂可订货,技术支持,直接渠道。可签保供合同 |
询价 | ||
恩XP |
2020+ |
QFN |
610 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
询价 | ||
恩XP |
16+ |
NA |
8800 |
诚信经营 |
询价 | ||
恩XP |
1715+ |
SOP |
251156 |
只做原装正品现货假一赔十! |
询价 | ||
恩XP |
24+ |
VFQFN-16 |
20 |
NXP一级代理商原装进口现货,假一赔十 |
询价 | ||
恩XP |
18+ |
QFN16 |
85600 |
保证进口原装可开17%增值税发票 |
询价 |
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