PCA9549BS数据手册恩XP中文资料规格书

描述 Description

Overview Archived content is no longer updated and is made available for historical reference only.
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled by the I²C-bus. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. Any individual A to B channel or combination of channels can be selected via the I²C-bus, determined by the contents of the programmable Control register. When the I²C-bus bit is HIGH (logic 1), the switch is on and data can flow from Port A to Port B, or vice versa. When the I²C-bus bit is LOW (logic 0), the switch is open, creating a high-impedance state between the two ports, which stops the data flow.
An active LOW reset input (RESET) allows the PCA9549 to recover from a situation where the I²C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus state machine and causes all the bits to be open, as does the internal power-on reset function.
Three address pins allow up to eight devices on the same bus.

特性 Features

•8-bit bus switch (CBT)

•5 Ω switch connection between two ports

•I²C-bus interface logic; compatible with SMBus standards

•Active LOW RESET input

•3 address pins allowing up to 8 devices on the I²C-bus

•Bit selection via I²C-bus, in any combination

•Power-up with all bits deselected

•Low Ron switches

•No glitch on power-up

•Supports hot insertion

•Low standby current

•Operating power supply voltage range of 2.3 V to 5.5 V

•5 V tolerant inputs

•0 Hz to 400 kHz clock frequency

•ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

•Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

•Packages offered: SO24, TSSOP24, HVQFN24