PCA9516A集成电路（IC）的信号缓冲器、中继器、分离器规格书PDF中文资料

DESCRIPTION

The PCA9516A is a CMOS integrated circuit intended for application in I2C and SMBus systems.

While retaining all the operating modes and features of the I2C system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.

The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9516A enables the system designer to divide the bus into five segments off of a hub where any segment to segment transition sees only one repeater delay.

FEATURES

• 5 channel, bi-directional buffer

• I2C-bus and SMBus compatible

• Active HIGH individual repeater enable input

• Open-drain input/outputs

• Lock-up free operation

• Supports arbitration and clock stretching across the repeater

• Accommodates standard mode and fast mode I2C devices and multiple masters

• Powered-off high impedance I2C pins

• Operating supply voltage range of 2.3 V to 3.6 V

• 5.5 V tolerant I2C and enable pins

• 0 kHz to 400 kHz clock frequency1

• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101.

• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA.

• Package offerings: SO16 and TSSOP16