PC87591E数据手册TI中文资料规格书

描述 Description

General Description
The National Semiconductor PC87591E, PC87591S and PC87591L are highly integrated, embedded controllers with an embedded-RISC core and integrated advanced functions. These devices are targeted for a wide range of portable applications that use the Low Pin Count (LPC) interface.Outstanding

特性 Features

■ Host interface, based on Intel’sLPC Interface Specification Revision 1.0, September 29th, 1997
■ PC01 Rev 1.0, and ACPI 2.0 compliant
■ 16-bit RISC core, with 2 Mbyte address space, and running at up to 20 MHz
■ Software and Hardware controlled clock throttling
■ Shared BIOS flash memory (internal and/or external)
■ Y2K-compliant RTC
■ 84/117 GPIO ports (for 128-pin/176-pin packages) with a variety of wake-up events
■ Extremely low current consumption in Idle mode
■ JTAG-based debugger interface
■ 128-pin and 176-pin options, in LQFP package (PC87591L is 176-pin only)Features
■ Processing Unit
—CompactRISC CR16B 16-bit embedded RISC processor core (the “core”)
—2 Mbyte address space
■ Internal Memory
—Up to 128 Kbytes of on-chip flash memory (4 Kbytes of ROM in the PC87591L)
—Supports BIOS (flash) memory sharing with PC host
—On-chip flash is field upgradable by host, CR16B, parallel interface or JTAG
—Boot blocks for both CR16B and Host Code
—Memory contents protection and security
—Hardware-protected boot zone with block protection circuit
—2K (PC87591E/L) or 4K of on-chip RAM (PC87591S)
—All memory types can hold both code and data
■ Expansion Memory (Optional in 176-pin package)
—Up to 1 Mbyte of additional code and data
—Supports BIOS (flash) memory sharing with PC host
—Supports external memory power-down mode
—Field upgradable with flash or SRAM devices
—Supports host-controlled code download and up date
—Bus Interface Unit (BIU)
   ❏ Three address zones for static devices (SRAM, ROM, flash, I/O)
   ❏ Configurable wait states and fast-read, single cycle bus cycles
   ❏ 8- or 16-bit wide bus
■ LPC System Interface
—Synchronous cycles, up to 33 MHz bus clock
—Serial IRQ
—I/O and Memory read and write cycles
—Bootable memory support
—Bus Master read and write cycles
—Reset input
—Base Address (BADDR) strap to determine the base address of the Index-Data register pair
—LPCPD andCLKRUN support
—FWH Transaction support
■ Security Function Support
—Random Number Generator (RNG)
—Full Random using temperature, voltage and system noise.
—Memory access protection Embedded Controller System Features
■ Host Bus Interface (HBI)
—Three host interface channels, typically used for the KBC, ACPI Private or Shared EC channels
—8042 KBC standard Interface (legacy 6016, 6416)
—Intel 80C51SL compatible
—IRQ1 and IRQ12 support
—Fast Gate A20 and Fast Host Reset via firmware
—PM interface port (legacy 6216, 6616)
—ACPI Embedded Controller with either Shared or Private interface
—IRQ, SMI or SCI generation