PA7128J-15数据手册TI中文资料规格书

描述 Description

General Description
The PA7128 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free design ers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7128 offers a versatile logic array architecture with 12 I/O pins, 14 input pins and 36 registers/latches (12 buried logic cells, 12 input registers/latches, 12 buried I/O registers/latches). Its logic array implements 50 sum-of-products logic functions that share 64 product terms. The PA7128’s logic and I/O cells (LCCs, IOCs) are extremely flexible offering up to three output functions per cell (a total of 36 for all 12 logic cells).

特性 Features

■ CMOS Electrically Erasable Technology
   − Reprogrammable in 28-pin DIP, SOIC and PLCC packages
■ Versatile Logic Array Architecture
   − 12 I/Os, 14 inputs, 36 registers/latches
   − Up to 36 logic cell output functions
   − PLA structure with true product-term sharing
   − Logic functions and registers can be I/O-buried
■ Flexible Logic Cell
   − Up to 3 output functions per logic cell
   − D,T and JK registers with special features
   − Independent or global clocks, resets, presets, clock polarity and output enables
   − Sum-of-products logic for output enables
■ High-Speed Commercial and Industrial Versions
   − As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX)
   − Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85 °C temperatures
■ Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications
   − Integration of multiple PLDs and random logic
   − Buried counters, complex state-machines
   − Comparitors, decoders, other wide-gate functions
■ Development and Programmer Support
   − ICT PLACE Development Software
   − Fitters for ABEL, CUPL and other software
   − Programming support by ICT PDS-3 and other popular third-party programmers.