Power Beads - PA2509NL Series

文件：334.47 Kbytes 页数：2 Pages

pulse

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC

文件：70.65 Kbytes 页数：10 Pages

PHI

飞利浦

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

文件：79.02 Kbytes 页数：10 Pages

PHI

飞利浦

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

文件：79.02 Kbytes 页数：10 Pages

PHI

飞利浦