8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 10-bit ADC

文件：307.72 Kbytes 页数：66 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC

文件：339.26 Kbytes 页数：69 Pages

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 10-bit ADC

文件：307.72 Kbytes 页数：66 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC

文件：339.26 Kbytes 页数：69 Pages

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 10-bit ADC

文件：307.72 Kbytes 页数：66 Pages

PHI

PHI

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC

文件：339.26 Kbytes 页数：69 Pages

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC

Overview The P89LPC952/954 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the Principal features\n8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.\n256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.\n8-input multiplexed 10-bit ADC with window co;

恩XP

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC

Overview The P89LPC952/954 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the Principal features\n8 kB/16 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.\n256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.\n8-input multiplexed 10-bit ADC with window co;

恩XP