P89C51RB2HBBD中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The P89C51RB2/RC2/RD2Hxx device contains a non-volatile 16KB/32KB/64KB Flash program memory that is both parallel programmable and serial In-System and In-Application Programmable. In-System Programming (ISP) allows the user to download new code while the microcontroller sits in the application.

FEATURES

• 80C51 Central Processing Unit

• On-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability

• Boot ROM contains low level Flash programming routines for downloading via the UART

• Can be programmed by the end-user application (IAP)

• Parallel programming with 87C51 compatible hardware interface to programmer

• Six clocks per machine cycle operation (standard)

• 12 clocks per machine cycle operation (optional)

• Speed up to 20 MHz with 6 clock cycles per machine cycle (40 MHz equivalent performance); up to 33 MHz with 12 clocks per machine cycle

• Fully static operation

• RAM expandable externally to 64 kbytes

• Four interrupt priority levels

• Seven interrupt sources

• Four 8-bit I/O ports

• Full-duplex enhanced UART

– Framing error detection

– Automatic address recognition

• Power control modes

– Clock can be stopped and resumed

– Idle mode

– Power down mode

• Programmable clock out

• Second DPTR register

• Asynchronous port reset

• Low EMI (inhibit ALE)

• Programmable Counter Array (PCA)

– PWM

– Capture/compare