P87C51MB2BA数据手册恩XP中文资料规格书

描述 Description

Overview The P87C51Mx2 represents the first microcontroller based on Philips Semiconductors? new 51MX core. The P87C51MC2 features 96 kbytes of OTP program memory and 3 kbytes of data SRAM, while the P87C51MB2 has 64 kbytes of OTP and 2 kbytes of RAM. In addition, both devices are equipped with a Programmable Counter Array (PCA), a watchdog timer that can be configured to different time ranges through SFR bits, as well as two enhanced UARTs and Serial Peripheral Interface (SPI).
Philips Semiconductors? 51MX (Memory eXtension) core is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. The linear address range of the 51MX has been expanded to support up to 8 Mbytes of program memory and 8 Mbytes of data memory. It retains full program code compatibility to enable design engineers to re-use 80C51 development tools, eliminating the need to move to a new, unfamiliar architecture. The 51MX core also retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced peripherals and Application Specific Integrated Circuits (ASICs).
The P87C51Mx2 provides greater functionality, increased performance and overall lower system cost. By offering an embedded memory solution combined with the enhancements to manage the memory extension, the P87C51Mx2 eliminates the need for software work-around. The increased program memory enables design engineers to develop more complex programs in a high-level language like C, for example, without struggling to contain the program within the traditional 64 kbytes of program memory. These enhancements also greatly improve C Language efficiency for code size below 64 kbytes.
The 51MX core is described in more detail in the 51MX Architecture Reference.

特性 Features

Key features
Extended features of the 51MX Core: 23-bit program memory space and 23-bit data memory space
Linear program and data address range expanded to support up to 8 Mbytes each
Program counter expanded to 23 bits
Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation
New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C compiler code efficiency in using pointers to access variables in different spaces

100pct. binary compatibility with the classic 80C51 so that existing code is completely reusable
Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
96 kbytes (MC2) or 64 kbytes (MB2) of on-chip OTP
3 kbytes (MC2) or 2 kbytes (MB2) of on-chip RAM
Programmable Counter Array (PCA)
Two full-duplex enhanced UARTs and Serial Peripheral Interface (SPI) communication modules
Key benefits
Increases program/data address range to 8 Mbytes each
Enhances performance and efficiency for C programs
Fully 80C51-compatible microcontroller
Provides seamless and compelling upgrade path from classic 80C51
Preserves 80C51 code base, investment/knowledge, and peripherals and ASICs
Supported by wide range of 80C51 development systems and programming tools vendors
The P87C51Mx2 makes it possible to develop applications at lower cost and with a reduced time-to-market
Complete features
Fully static
Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
96 kbytes or 64 kbytes of on-chip OTP
3 kbytes or 2 kbytes of on-chip RAM
23-bit program memory space and 23-bit data memory space
Four-level interrupt priority
34 I/O lines (5 ports)
Three Timers: Timer0, Timer1 and Timer2
Two full-duplex enhanced UARTs with baud rate generator
Framing error detection
Automatic address recognition
Supports industry-standard Serial Peripheral Interface (SPI) with a baud rate up to 6 Mbits/s
Power control modes
Clock can be stopped and resumed
Idle mode
Power down mode with advanced clock control
Second DPTR register
Asynchronous port reset
Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five Capture/Compare modules
Low EMI (inhibit ALE)
Watchdog timer with programmable prescaler for different time ranges (compatible with 8xC66x with added prescaler)