P80C31SBAA数据手册恩XP中文资料规格书

描述 Description

The Philips 80C31/32 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2.7 V to 5.5 V.\r
\r
The 80C31/32 ROMless devices contain a 128 ? 8 RAM/256 ? 8 RAM, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.\r
\r
In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reduction-idle mode and power-down mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped.

特性 Features

• 8051 Central Processing Unit\r
– 128 × 8 RAM (80C31)\r
– 256 × 8 RAM (80C32)\r
– Three 16-bit counter/timers\r
– Boolean processor\r
– Full static operation\r
– Low voltage (2.7 V to 5.5 V@ 16 MHz) operation\r
• Memory addressing capability\r
– 64k ROM and 64k RAM\r
• Power control modes:\r
– Clock can be stopped and resumed\r
– Idle mode\r
– Power-down mode\r
• CMOS and TTL compatible\r
• TWO speed ranges at VCC = 5 V\r
– 0 to 16 MHz\r
– 0 to 33 MHz\r
• Three package styles\r
• Extended temperature ranges\r
• Dual Data Pointers\r
• 4 level priority interrupt\r
• 6 interrupt sources\r
• Four 8-bit I/O ports\r
• Full–duplex enhanced UART\r
– Framing error detection\r
– Automatic address recognition\r
• Programmable clock out\r
• Asynchronous port reset\r
• Low EMI (inhibit ALE)\r
• Wake-up from Power Down by an external interrupt