P74AVCH4T245QPWRQ1中文资料德州仪器数据手册PDF规格书

1 Features

• Control inputs VIH/VIL levels are referenced to

VCCA voltage

• Fully configurable dual-rail design allows each port

to operate over the full 1.08V to 3.6V power-supply

range

• Ioff supports partial power-down-mode operation

• Bus hold on data inputs eliminates the need for

external pull-up/pull-down resistors

• Supports data rate up to:

– 500Mbps (1.08V to 3.6V translation)

• Latch-up performance exceeds 100mA per JESD

78, class II

• ESD protection exceeds JESD 22:

– 8000V Human Body Model (A114-A)

– 200V Machine Model (A115-A)

– 1000V Charged-Device Model (C101)

2 Applications

• Personal electronics

• Industrial

• Enterprise

• Telecom

3 Description

This 4-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The A port

is designed to track VCCA. VCCA accepts any supply

voltage from 1.08V to 3.6V. The B port is designed

to track VCCB. VCCB accepts any supply voltage from

1.08V to 3.6V. The SN74AVCH4T245-Q1 is optimized

to operate with VCCA/VCCB set at 1.08V to 3.6V.

It is operational with VCCA/VCCB as low as 1.08V.

This allows for universal low voltage bidirectional

translation between any of the 1.2V, 1.5V, 1.8V, 2.5V,

and 3.3V voltage nodes.

The SN74AVCH4T245-Q1 is designed for

asynchronous communication between two data

buses. The logic levels of the direction-control (DIR)

input and the output-enable (OE) input activate either

the B-port outputs or the A-port outputs or place

both output ports into the high-impedance mode. The

device transmits data from the A bus to the B bus

when the B-port outputs are activated, and from the

B bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports

is always active and must have a logic HIGH or LOW

level applied to prevent excess ICC and ICCZ.

The SN74AVCH4T245-Q1 device control pins (1DIR,

2DIR, 1OE, and 2OE) are supplied by VCCA.

This device is fully specified for partial-power-down

applications using Ioff. The Ioff circuitry disables

the outputs, preventing damaging current backflow

through the device when it is powered down.

The VCC isolation feature is designed so that if either

VCC input is at GND, then both ports are in the

high-impedance state. The bus-hold circuitry on the

powered-up side always stays active.

Active bus-hold circuitry holds unused or undriven

data inputs at a valid logic state. Use of pull-up or

pull-down resistors with the bus-hold circuitry is not

recommended. The bus-hold circuitry on the poweredup

side always stays active.

To put the device in the high-impedance state

during power up or power down, tie the OE pin to

VCC through a pull-up resistor; the current-sinking

capability of the driver determines the minimum value

of the resistor.