P2V28S20ATP-7中文资料世界先进数据手册PDF规格书

DESCRIPTION P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.

FEATURES

- Single 3.3V ±0.3V power supply

- Max. Clock frequency -7:143MHz/-75:133MHz/-8:100MHz

- Fully synchronous operation referenced to clock rising edge

- 4-bank operation controlled by BA0,BA1(Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/FP (programmable)

- Burst type- Sequential and interleave burst (programmable)

- Byte Control- DQML and DQMU (P2V28S40ATP)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- Auto and self refresh

- 4096 refresh cycles /64ms

- LVTTL Interface

- Package

P2V28S20ATP/30ATP/40ATP

400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch