丝印：OP07CS；Package：SOP-8；Low offset single operational amplifier

Main feature Maximum offset voltage 150uV MAX Low offset current Iio=1.3nA typ The working voltage range is ±3V to ±20V.

文件：697.33 Kbytes 页数：5 Pages

UMW

友台半导体

丝印：OP07CS；Package：SOP-8；Low offset single operational amplifier

Main feature Maximum offset voltage 150uV MAX Low offset current Iio=1.3nA typ The working voltage range is ±3V to ±20V.

文件：697.33 Kbytes 页数：5 Pages

UMW

友台半导体

Ultralow Offset Voltage Dual Operational Amplifier

GENERAL DESCRIPTION The OP07 has very low input offset voltage (75 μV maximum for OP07E) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (±4 nA for the OP07E) and high open-

文件：448.68 Kbytes 页数：10 Pages

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亚德诺

Ultralow Offset Voltage Operational Amplifier

FEATURES Low VOS: 75 μV maximum Low VOS drift: 1.3 μV/°C maximum Ultrastable vs. time: 1.5 μV per month maximum Low noise: 0.6 μV p-p maximum Wide input voltage range: ±14 V typical Wide supply voltage range: ±3 V to ±18 V 125°C temperature-tested dice APPLICATIONS Wireless base station c

文件：232.37 Kbytes 页数：16 Pages

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Ultralow Offset Voltage Operational Amplifier

GENERAL DESCRIPTION The OP-07 has very low input offset voltage (25 μV maximum for OP07A) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP-07 also features low input bias current (±2 nA for the OP-07A) and high op

文件：239.08 Kbytes 页数：16 Pages

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亚德诺

Ultralow Offset Voltage Operational Amplifier

GENERAL DESCRIPTION The OP-07 has very low input offset voltage (25 μV maximum for OP07A) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP-07 also features low input bias current (±2 nA for the OP-07A) and high op

文件：239.08 Kbytes 页数：16 Pages

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亚德诺

Ultralow Offset Voltage Operational Amplifier

GENERAL DESCRIPTION The OP-07 has very low input offset voltage (25 μV maximum for OP07A) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP-07 also features low input bias current (±2 nA for the OP-07A) and high op

文件：239.08 Kbytes 页数：16 Pages

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亚德诺

Ultralow Offset Voltage Operational Amplifier

GENERAL DESCRIPTION The OP-07 has very low input offset voltage (25 μV maximum for OP07A) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP-07 also features low input bias current (±2 nA for the OP-07A) and high op

文件：239.08 Kbytes 页数：16 Pages

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亚德诺

Ultralow Offset Voltage Operational Amplifier

GENERAL DESCRIPTION The OP-07 has very low input offset voltage (25 μV maximum for OP07A) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP-07 also features low input bias current (±2 nA for the OP-07A) and high op

文件：239.08 Kbytes 页数：16 Pages

AD

亚德诺

Ultralow Offset Voltage Operational Amplifier

GENERAL DESCRIPTION The OP-07 has very low input offset voltage (25 μV maximum for OP07A) that is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP-07 also features low input bias current (±2 nA for the OP-07A) and high op

文件：239.08 Kbytes 页数：16 Pages

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亚德诺