2M x 36 and 4M x 18 72Mb, FLOW THROUGH NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MO

文件：1.39966 Mbytes 页数：38 Pages

ISSI

矽成半导体