NT68P62中文资料ETC数据手册PDF规格书

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General Description

The NT68P62 is a new generation of monitor mC for autosync and digital control applications. Particularly, this chip supports various and efficient functions to allow users to easily develop USB monitors. It contains the 6502 8-bit CPU core, 512 bytes of RAM used as working RAM and stack area, 32K bytes of OTP ROM, 13-channel of 8-bit PWM D/A converters, 4-channel A/D converters for keys detection which can save I/O pins, one 8-bit pre-loadable base timer, internal Hsync and Vsync signals processor, and a watch-dog timer which prevents the system from abnormal operation and two I2C bus interface. The user can store EDID data in the 128 bytes of RAM for DDC1/2B, so that user can reduce a dedicated EEPROM for EDID. And Half frequency output function can save external oneshot circuit. All of these designs are committed to offer our user saving component cost. The 42 pin S-DIP IC provides two additional I/O pins – port40 & port41, Part number NT68P62U represents the S-DIP IC. For future reference, port40 & port42 is only available for the 42 pin S-DIP IC.

特性 Features

■ Operating voltage range: 4.5V to 5.5V

■ CMOS technology for low power consumption

■ 6502 8-bit CMOS CPU core

■ 8 MHz operation frequency

■ 32K bytes of OTP (one time programming) ROM

■ 512 bytes of RAM

■ One 8-bit base timer

■ 13 channels of 8-bit PWM outputs with 5V open drain

■ 4 channel A/D converters with 6-bit resolution

■ 25 bi-directional I/O port pins (8 dedicated I/O pins)

■ Hsync/vsync signals processor for separate & composite signal, including hardware sync signals polarity detection and freq. counters with 2 sets of Hsync counting interval

■ Hsync/Vsync polarity controlled output, 5 selectable free run output signals and self-test patterns, automute function, half freq. I/O function

■ Two built-in I2C bus interfaces support VESA DDC1/2B+

■ Two layers of interrupt management

■ NMI interrupt sources

- INTE0 (External INT with selectable edge trigger)

- INTMUTE (Auto Mute Activated)

IRQ interrupt sources

- INTS0/1 (SCL Go-low INT)

- INTA0/1 (Slave Address Matched INT)

- INTTX0/1 (Shift Register INT)

- INTRX0/1 (Shift Register INT)

- INTNAK0/1 (No Acknowledge)

- INTSTOP0/1 (Stop Condition Occurred INT)

- INTE1 (External INT with Selectable Edge Trigger)

- INTV (VSYNC INT)

- INTMR (Base Timer INT)

- INTADC (AD Conversion Done INT)

■ Hardware watch-dog timer function

■ 40-pin P-DIP and 42-pin S-DIP packages