NT5SV16M16AT-75B中文资料256Mb Synchronous DRAM数据手册Nanya规格书

描述 Description

The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT are four-bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’s advanced 256Mbit single transistor CMOS DRAM process technology.

特性 Features

• High Performance: (TABLE)
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0/BA1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
• 8192 refresh cycles/64ms
• Random Column Address every CK (1-N Rule)
• Single 3.3V ± 0.3V Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
• -7K parts for PC133 2-2-2 operation
  -75B parts for PC133 3-3-3 operation
  -8B parts for PC100 2-2-2 operation