NT5DS64M8DS-6K中文资料南亚科数据手册PDF规格书

Feature

z Power Supply Voltage:

VDD=VDDQ=2.5V±0.2V (DDR-333)

VDD=VDDQ=2.6V±0.1V (DDR-400/500)

z 4 internal memory banks for concurrent operation.

z CAS Latency: 2, 2.5 and 3

z Double Data Rate Architecture

z Bidirectional data strobe (DQS) is transmitted and

received with data, to be used in capturing data at the

receiver.

z Industrial grade device support -40℃~95℃ Operating

Temperature (-75I/-6KI/5TI)

z 2KB page size for all configurations.

z DQS is edge-aligned with data for reads and is

center-aligned with data for WRITEs

z Differential clock inputs (CK and CK)

z Data mask (DM) for write data

z DLL aligns DQ and DQS transition with CK transitions.

z Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

z Burst Lengths: 2, 4 or 8

z Auto Precharge option for each burst access

z Auto-Refresh and Self-Refresh Mode

z 7.8 µs max. Average Periodic Refresh Interval

z 2.5V (SSTL_2 compatible) I/O

z RoHS compliance

z JEDEC Standard Compliance

z Packages: 66 pin TSOPII