NT5CC256M16EP-DIB中文资料南亚科数据手册PDF规格书

 Basis DDR3 Compliant

-8n Prefetch Architecture

-Differential C lock (   and Data Strobe(DQS/   

-Double data rate on DQs, DQS and DM

 Data Integrity

-Auto Self Refresh ( A SR) by DRAM built in T S

-Auto Refresh and Self Refresh Mode s

 Power Saving Mode

-Power Down Mode

 Signal Integrity

-Configurable DS for system compatibility

-Configurable On Die Termination

-ZQ Calibration for DS/ODT impedance accuracy via

external ZQ pad (240 ohm 1)

 Signal Synchronization

-Write Leveling via MR settings 5

-Read Leveling via MPR

 Interface and Power Supply

-SSTL_15 for DDR3:VDD/VDDQ= 1.5V ((±0.075V

-SSTL_135 2 for DDR3L:V DD/VDDQ= 1.35V 0.067/+0.1V