NCSA25D34中文资料时钟芯片,Clock Buffer数据手册NewCoSemi规格书

描述 Description

The NCSA25D34 is a highly versatile, high-performance, 4-output differential AEC-Q100 qualified fanout buffer and level translator which can operate up to 3.1GHz with ultra-low additive jitter.The input clock can be selected from two universal differential or single-ended inputs, or one crystal input which can be overdriven by external single-ended clock. Crystal input frequencies from 8MHz to 50MHz are supported.A 3:1 input MUX controlled by two external pins is implemented to distribute the selected input clock to two banks of 2 differential outputs and one LVCMOS reference output.Both banks of differential outputs can be configured as LVPECL, LVDS, HCSL driver mode or disabled mode by two external pins.The NCSA25D34 operates from a 3.3V core supply and 3 independent 3.3V or 2.5V driver output supply, and does not have power supply sequencing requirements between the core and output supply domains.

特性 Features

• High-performance clock buffer with Ultra-low noise floor of -167 dBc/Hz
•Level translation from 3.3v core supply to output Supply of 3.3V or 2.5V
•3：1 Input clock multiplexer which is selectable through input pins.
• Two universal inputs operate up to 3.1GHz and can accept LVPECL, LVDS, CML, SSTL, HSTL, or HCSL signals
• Both differential and single-ended input are supported
• Support either DC or AC-coupled input interface
• Crystal input frequencies from 8MHz to 50MHz
• Crystal overdrive mode with input frequency up to 250MHz
•4 differential output with two output supply banks
• Support LVPECL, LVDS, HCSL or Hi-Z output mode
• Ultra-low additive jitter (at 156.25MHz) 40 fs RMS (10K to 20MHz, LVPECL) 52 fs RMS (10K to 20MHz, LVDS)
•Highs PSRR (at 156.25 MHz)-67 dBc LVPECL, -79 dBc LVDS
•LVCMOS reference clock output with independent VCCOC supply and synchronous enable input