NCS23381中文资料时钟芯片,PLL数据手册NewCoSemi规格书

描述 Description

NCS23381 jitter attenuators / clock multiplier combines APLL and DPLL to deliver ultra-low jitter for high performance applications like wireless infrastructure. All PLL components are fully-integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. It features 4 differential or singleended clock inputs and 12 differential or 24 single-ended clock outputs. Furthermore, 4 independent APLL / DPLL outputs can be locked to any of the inputs and sent to any of the chip outputs. Each output can be configured as LVDS, LVPECL or two single-ended LVCMOS. In addition, each output clock phase can be adjusted dynamically. NCS23381 supports free-run, synchronous and holdover modes as well as enhanced automatic or manual hitless switching between input clocks. It is programmable by I2C or SPI serial interface. NCS23381 is capable of generating any combination of output frequency from any input frequency as specified in the datasheet.

特性 Features

•Generate any combination of output frequencies from any input frequency
•External XTAL or XO reference frequency from 48MHz to 54MHz
•Supports free-run, synchronous (Lock input) and holdover modes as well as enhanced hitless switching
•Supports up to 4 independent APLL/DPLL loops and 12 outputs
•Supports 4 differential or single-ended clock inputs
•   Meets G.8262, G.8262.1 EEC Standards
•   Status monitoring (LOS, OOF, LOL)
•Zero delay mode
•Supports JESD204B/C
•Serial Interface: I2C or SPI
•Input frequency range
• Differential: 8 kHz to 750MHz
• LVCMOS: 8 kHz to 250 MHz
•Output frequency range
• Differential: 8 kHz to 2 GHz
• LVCMOS: 8 kHz to 250 MHz
•Highly configurable outputs format
• compatible with LVDS, LVPECL, LVCMOS,
• CML and HCSL with programmable signal
• amplitude and output common voltage
•Independent output clock supply pins: 3.3V, 2.5V, or 1.8V.
•Package: QFN 64pin (9mm x 9mm)