NBSG14中文资料SiGe Clock / Data Fanout Buffer, 1:4 Differential, 2.5 V / 3.3 V, with RSECL Outputs数据手册ONSEMI规格书

描述 Description

The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for ultra-low skew and jitter.Inputs incorporate internal 50-ohm termination resistors and acceptNECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.

特性 Features

• Maximum Input Clock Frequency up to 12 GHz
• Maximum Input Data Rate up to 12 Gb/s Typical
• 50 Ω Internal Input Termination Resistors
• 30 ps Typical Rise and Fall Times
• 125 ps Typical Propagation Delay
• RSPECL Output with Operating Range: V = 2.375 V to 3.465 V with VEE = 0 V
• RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
• RSECL Output Level (400 mV Peak-to-Peak Output),
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices

简介

NBSG14属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的NBSG14时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。