Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t

文件：140.22 Kbytes 页数：18 Pages

PHI

PHI

Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t

文件：140.22 Kbytes 页数：18 Pages

PHI

PHI

Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t

文件：140.22 Kbytes 页数：18 Pages

PHI

PHI

9-Bit D-Type Flip-Flop

文件：158.08 Kbytes 页数：8 Pages

NSC

国半

9-Bit D-Type Flip-Flop

General Description The 74F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. Features ■ 3-STATE outputs ■ Clock Enable and Clear

文件：52.03 Kbytes 页数：6 Pages

FAIRCHILD

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