8-bit shift register with input storage registers 3-State

DESCRIPTION The 74F598 consists of an 8–bit storage register feeding a parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both the storage register and shift register have positive edge–triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asyn

文件：115.65 Kbytes 页数：14 Pages

PHI

飞利浦

8-bit shift register with input storage registers 3-State

恩XP

恩智浦

8-bit shift register with input storage registers 3-State

DESCRIPTION The 74F598 consists of an 8–bit storage register feeding a parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both the storage register and shift register have positive edge–triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asyn

文件：115.65 Kbytes 页数：14 Pages

PHI

飞利浦

8-bit shift register with input storage registers 3-State

DESCRIPTION The 74F598 consists of an 8–bit storage register feeding a parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both the storage register and shift register have positive edge–triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asyn

文件：115.65 Kbytes 页数：14 Pages

PHI

飞利浦