8-bit shift register with input storage registers

DESCRIPTION The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register. The storage register and shift register have separate positive edge triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous

文件：97.06 Kbytes 页数：12 Pages

PHI

飞利浦

8-bit shift register with input storage registers

DESCRIPTION The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register. The storage register and shift register have separate positive edge triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous

文件：97.06 Kbytes 页数：12 Pages

PHI

飞利浦

8-bit shift register with input storage registers

DESCRIPTION The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register. The storage register and shift register have separate positive edge triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous

文件：97.06 Kbytes 页数：12 Pages

PHI

飞利浦

TSSOP20

Nuvoton

新唐科技

上传：深圳市惠芯源电子有限公司

Nuvoton

新唐科技

上传：深圳市云中傲科技有限公司