N74F552N中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the Output Enable returns to High after reading the output port. Each register has a separate Output Enable (OEAS, OEBR) for its 3-State buffer. The separate Clocks, Flags and Enables provide considerable flexibility as I/O ports for demand-response data transfer.

FEATURES

• 8-bit bidirectional I/O port with handshake

• Register status flag flip-flops

• Separate clock enable and output enable

• Parity generation and parity check

• B outputs and parity output sink 64mA