4-bit cascadable shift register 3-State

DESCRIPTION The 74F395 is a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs. The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input. When PE is High, data is loaded from the Parallel Data inputs (D0–D3

文件：65.33 Kbytes 页数：7 Pages

PHI

飞利浦

4-bit cascadable shift register 3-State

恩XP

4-bit cascadable shift register 3-State

DESCRIPTION The 74F395 is a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs. The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input. When PE is High, data is loaded from the Parallel Data inputs (D0–D3

文件：65.33 Kbytes 页数：7 Pages

PHI

飞利浦

4-bit cascadable shift register 3-State

DESCRIPTION The 74F395 is a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs. The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input. When PE is High, data is loaded from the Parallel Data inputs (D0–D3

文件：65.33 Kbytes 页数：7 Pages

PHI

飞利浦

High Q, high self-resonant frequency Varnish coated

文件：429.04 Kbytes 页数：1 Pages

Bourns

伯恩斯