Arithmetic Logic Unit

DESCRIPTION The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Three additional Select (S0–S2) input codes force the Function outputs Low or High. Carry Propagate (P) and Generate (G) ouputs are provided for use with the 74F182 Carry Look Ahead Generato

文件：82.32 Kbytes 页数：7 Pages

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Arithmetic Logic Unit

DESCRIPTION The 74F381 performs three arithmetic and three logic operations on two 4-bit words, A and B. Three additional Select (S0–S2) input codes force the Function outputs Low or High. Carry Propagate (P) and Generate (G) ouputs are provided for use with the 74F182 Carry Look Ahead Generato

文件：82.32 Kbytes 页数：7 Pages

PHI

PHI

Arithmetic Logic Unit

DESCRIPTION The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select (S0–S2) input codes force the Function outputs Low or High. An overflow output is provided for convenience in Two’s Complement arithmetic. FEATURES • Performs six

文件：121.82 Kbytes 页数：12 Pages

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PHI

Arithmetic Logic Unit

DESCRIPTION The 74F382 performs three arithmetic and three logic operations on two 4-bit words, A and B. Two additional Select (S0–S2) input codes force the Function outputs Low or High. An overflow output is provided for convenience in Two’s Complement arithmetic. FEATURES • Performs six

文件：121.82 Kbytes 页数：12 Pages

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PHI

Quad serial adder/subtractor

DESCRIPTION The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. Th

文件：64.3 Kbytes 页数：6 Pages

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PHI

Quad serial adder/subtractor

DESCRIPTION The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. Th

文件：64.3 Kbytes 页数：6 Pages

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Quad futurebus backplane transceiver

DESCRIPTION The 74F3893 is a quad backplane transceivers and is intended to be used in very high speed bus systems. The 74F3893 interfaces to ‘Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to

文件：72.92 Kbytes 页数：10 Pages

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Quad 2-input NAND buffer open collector

FEATURE • Industrial temperature range available (–40°C to +85°C)

文件：70.22 Kbytes 页数：8 Pages

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PHI

Quad 2-input NAND buffer open collector

FEATURE • Industrial temperature range available (–40°C to +85°C)

文件：70.22 Kbytes 页数：8 Pages

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Arithmetic Logic Unit

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