N74F378D中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74F378 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low.

The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transformed to the corresponding flop-flop’s Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.

FEATURES

• 6-bit high-speed parallel register

• Positive edge-triggered D-type inputs

• Fully buffered common Clock and Enable inputs

• Input clamp diodes limit high speed termination effects

• Fully TTL and CMOS compatible