N74F2952N中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74F2952 and 74F2953 are 8-bit registered transceivers. Two 8-bit back-to-back registers store data flowing in both directions between two bi-directional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (CEXX) is Low. The data is then present at the 3-State output buffers, but is only accessible when the Output Enable (OEXX) is Low. Data flow from ‘A’ inputs to ‘B’ outputs is the same as for ‘B’ inputs to ‘A’ outputs.

FEATURES

• 8-bit registered transceivers

• Two 8-bit, back-to-back registers store data moving in both directions between two bidirectional buses

• Separate Clock, Clock Enable and 3-State Enable provided for each register

• 74F2952 non-inverting

• 74F2953 inverting

• AM2952/2953 functional equivalent

• ‘A’ outputs sink 24mA and source 3mA

• ‘B’ outputs sink 64mA and source 15mA

• 300 mil wide 24-pin Slim DIP package