N74F256D规格书应用电路批发采购飞利浦-114ic电子网

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型号	下载订购	功能描述	制造商上传企业	LOGO
N74F256D	文件：104.12 Kbytes Page：12 Pages	Dual addressable latch DESCRIPTION The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. FEATURES • Combi 文件：104.12 Kbytes 页数：12 Pages	PHI 飞利浦	PHI
N74F256D	文件：300 bytes Page：1 Pages	Dual addressable latch	恩XP 恩智浦	恩XP
N74F256N	文件：104.12 Kbytes Page：12 Pages	Dual addressable latch DESCRIPTION The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. FEATURES • Combi 文件：104.12 Kbytes 页数：12 Pages	PHI 飞利浦	PHI
74F256	文件：104.12 Kbytes Page：12 Pages	Dual addressable latch DESCRIPTION The 74F256 dual addressable latch has four distinct modes of operation which are selectable by controlling the Master Reset (MR) and Enable (E) inputs (see Function Table). In the addressable latch mode, data at the Data inputs is written into the addressed latches. FEATURES • Combi 文件：104.12 Kbytes 页数：12 Pages	PHI 飞利浦	PHI

更多N74F256D供应商更新时间2025-10-11 13:30:00