Hex D flip-flops

DESCRIPTION The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup ti

文件：75.93 Kbytes 页数：8 Pages

PHI

飞利浦

Hex D flip-flops

DESCRIPTION\nThe 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time b • Six edge-triggered D-type flip-flops\n• Buffered common Clock\n• Buffered, asynchronous Master Reset ;

恩XP

HEX D-TYPE FLIP-FLOP WITH CLEAR

文件：69.09 Kbytes 页数：5 Pages

TI

德州仪器

HEX D-TYPE FLIP-FLOP WITH CLEAR

文件：69.09 Kbytes 页数：5 Pages

TI

德州仪器

HEX D-TYPE FLIP-FLOP WITH CLEAR

文件：410.46 Kbytes 页数：11 Pages

TI

德州仪器