N74ALS273N数据手册恩XP中文资料规格书

描述 Description

DESCRIPTION
The 74ALS273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output.FEATURES
• Eight edge-triggered D-type flip-flops
• Buffered common clock
• Buffered asynchronous master reset
• See 74ALS377 for clock enable version
• See 74ALS373 for transparent latch version
• See 74ALS374 for 3-State version

特性 Features

• Eight edge-triggered D-type flip-flops
• Buffered common clock
• Buffered asynchronous master reset
• See 74ALS377 for clock enable version
• See 74ALS373 for transparent latch version
• See 74ALS374 for 3-State version