MX9691L中文资料​​​​​​​​​​​​旺宏电子数据手册PDF规格书

GENERAL DESCRIPTION

The Macronixs Solid State Disk controller MX9691L is a wide-range supply voltage(3.3Volt~5Volt) and fully integrated flash memory controller that provides all the control logic for PCMCIA/True IDE host and flash memory. The MX9691L combines 1KB dual-port buffer and buffer manager, integrated MX93011 DSP core, and a complete host interface for both the PC Card ATA and True IDE standard.

FEATURE

Host Interface

• PCMCIA 2.1 and PC Card ATA standard compatible.

- Memory mapped or I/O operation.

• Compatible with all PC Card Services and Socket Service.

• Fast ATA host-to-buffer burst transfer rates up to 20MB/sec. which support PIO mode 4(16.6MB/sec) and DMA mode 2(16.6MB/sec).

• Automatic sensing of PCMCIA or True IDE host inter face.

• Integrated PCMCIA attribute memory of 256 bytes (CIS) - CIS and Buffer RAM use same SRAM area to simplify internal bus design

• PCMCIA card configuration register support.

• Polarity control for Host reset signal.

• PCMCIA twin card support.

• PCMCIA based ATA address decode support.

• Emulate the IBM task file for PC/AT.

• Separate status for Host reset signal and Host program reset.

• Separate Host and Disk interrupt pins.

Flash Memory Interface

• Support all the control signals to execute read/ write/ erase operation for flash memory.

• Flexible Disk Capacity Configuration for series type or linear type flash memory

- Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit linear type flash memory.

- Upto 1GB(unformatted) capacity for 32 pcs. 256Mbit series type flash memory.

• Flash Memory Power Down or write protect control support.

• Flash Memory Ready/Busy status detect.

• Inverted data bus control to reduce flash memory program/erase operation in DOS FAT and ECC code field.

• Optional store firmware in flash memory array w/o external ROM while MXICs MX29F1610(linear type) used.

- Allow code fetch in Shadow ROM during flash memory program or erase.

Buffer RAM Manager

• Dual port circular Buffer RAM control

• 1KB data Buffer RAM.

• Automatically correct error data in Buffer RAM.

- Single word error correct and double word detect.

• Provide logic to speed up Buffer RAM access.

• Support 8 bit as well as 16 bit transfer on host bus.

DSP core

• High performance MX93011 DSP (21Mips) core.

• 4KB Internal RAM(direct access).

• 2KB Internal expansion RAM(indirect access) for store data or shadow ROM space.

• ICE debugging mode supported to ease system verification.

• Lower power and automatic power saving operation.

- Automatic Standby Mode. (Operating Current < 10mA, VCC=5.5V), wake-up by interrupt signal.

- Very Low Operating Current Sleep Mode.

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Technology

• 128 pin LQFP(14X14X1.4 mm3)

• 128 pin TQFP(14X14X1.0 mm3)

• 0.6um Low-power, High-speed CMOS technology.

• 5Volt ± 10 or 3.3Volt ± 5.

Utility Support

• Provide integrated test environment with 82365SL-compatible adaptor.

• Firmware upload from host and allows easy upgrade for custom feature.

• Physical devices test cover basic PCB test after assembly and more detial analysis.

• Logical sector test cover SSD functionality and data transfer test.