MVF30NN152CKU26中文资料恩XP数据手册PDF规格书

特性 Features

• Operating characteristics

– Voltage range 3 V to 3.6 V

– Temperature range(ambient) -40 °C to 85 °C

• ARM® Cortex® A5 Core features

– Up to 500 MHz ARM Cortex A5

– 32 KB/32 KB I/D L1 Cache

– 1.6 DMIPS/MHz based on ARMv7 architecture

– NEON™ MPE (Media Processing Engine) Coprocessor

– Double Precision Floating Point Unit

– 512 KB L2 cache (on selected part numbers only)

• ARM Cortex M4 Core features

– Up to 167 MHz ARM Cortex M4

– Integrated DSP capability

– 64 KB Tightly Coupled Memory (TCM)

– 16 KB/16 KB I/D L1 Cache

– 1.25 DMIPS/MHz based on ARMv7 architecture

• Clocks

– 24 MHz crystal oscillator

– 32 kHz crystal oscillator

– Internal reference clocks (128 KHz and 24 MHz)

– Phase Locked Loops (PLLs)

– Low Jitter Digital PLLs

• System debug, protection, and power management

– Various stop, wait, and run modes to provide low

power based on application needs

– Peripheral clock enable register can disable clocks to

unused modules, thereby reducing currents

– Low voltage warning and detect with selectable trip

points

– Illegal opcode and illegal address detection with

programmable reset or processor exception response

– Hardware CRC module to support fast cyclic

redundancy checks (CRC)

– 128-bit unique chip identifier

– Hardware watchdog

– External Watchdog Monitor (EWM)

– Dual DMA controller with 32 channels (with DMAMUX)

• Debug

– Standard JTAG

– 16-bit Trace port

• Timers

– Motor control/general purpose timer (FTM)

– Periodic Interrupt Timers (PITs)

– Low-power timer (LPTMR0)

– IEEE 1588 Timer per MAC interface (part of

Ethernet Subsystem)

• Communications

– Six Universal asynchronous receivers/transmitters

(UART)/Serial communications interface (SCI) with

LIN, ISO7816, IrDA, and hardware flow control

– Four Deserial Serial peripheral interface (DSPI)

– Four Inter-Integrated Circuit (I2C) with SMBUS

support

– Dual USB OTG Controller + PHY

– Dual 4/8 bit Secure Digital Host controller

– Dual 10/100 Ethernet with L2 Switch (IEEE 1588)

– Dual FlexCAN3

• Security

– ARM TrustZone including the TZ architecture

– Cryptographic Acceleration and Assurance Module,

incorporates 16 KB secure RAM (CAAM)

– Secure Non-Volatile Storage, including Secure Real

Time Clock (SNVS)

– Real Time Integrity Checker (RTIC)

– Tamper detection - supported by external pins, onchip

clock monitors, voltage and temperature

tampers

– TrustZone Watchdog (TZ WDOG)

– Trust Zone Address Space Controller

– Central Security Unit

– Secure JTAG

– High Assurance Boot (HAB) with support for

encrypted boot

• Memory Interfaces

– 8/16 bit DRAM Controller with support for

LPDDR2/DDR3 - Up to 400 MHz (ECC supported

for 8-bit only and not 16-bit)

– 8/16 bit NAND Flash controller with ECC

– 8/16/32 bit External bus (Flexbus)

– Dual Quad SPI with XIP (Execute-In-Place)

• Display and Video

– Dual Display Control Unit (DCU) with support for color TFT display up to SVGA

– Segmented LCD (3V Glass only) configurable as 40x4, 38x8, and 36x6

– Video Interface Unit (VIU) for camera

– VideoADC

• Analog

– Dual 12-bit SAR ADC with 1MS/s

– Dual 12-bit DAC

• Audio

– Four Synchronous Audio Interface (SAI)

– Enhanced Serial Audio Interface (ESAI)

– Sony Philips Digital Interface (SPDIF), Rx and Tx

– Asynchronous Sample Rate Converter (ASRC)

• Human-Machine Interface (HMI)

– GPIO pins with interrupt support, DMA request capability, digital glitch filter.

– Hysteresis and configurable pull up/down device on all input pins

– Configurable slew rate and drive strength on all output pins

• On-Chip Memory

– 512 KB On-chip SRAM with ECC

– 1 MB On-chip graphics SRAM (no ECC). This depends on the part selected. Alternate configuration could be 512 KB

graphics and 512 KB L2 cache.

– 96 KB Boot ROM