MT9041中文资料T1/E1 System Synchronizer数据手册Microchip规格书

描述 Description

The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.048 MHz, 1.544 MHz, or 8 kHz input reference. The MT9041B is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, Stratum 4, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these specifications.

特性 Features

• Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces
• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces
• Selectable 1.544 MHz, 2.048 MHz or 8 kHz input reference signals
• Provides C1.5, C2, C3, C4, C8 and C16 output clock signals
• Provides 3 different styles of 8 KHz framing pulses
• Attenuates wander from 1.9 Hz

简介

MT9041属于集成电路（IC）的电信。由制造生产的MT9041电信电信接口集成电路 (IC) 为通信网络接口提供特定功能和控制，例如以太网切换、线路驱动器、ISDN、放大器、通道扩展器、数字锁相环、DTMF、音频发生器和解码器、回声消除、检测器和发生器、DDA、电话线路监控器和主叫号码标识。