MT8940AE中文资料ISO-CMOS ST-BUS FAMILY T1/CEPT Digital Trunk PLL数据手册Mitel规格书

描述 Description

The MT8940 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing signals for the CEPT transmission link and the ST-BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal.

特性 Features

• Provides T1 clock at 1.544 MHz locked to input frame pulse
• Sources CEPT (30+2) Digital Trunk/ST-BUS clock and timing signals locked to internal or external 8 kHz signal
• TTL compatible logic inputs and outputs
• Uncommitted 2-input NAND gate
• Single 5 volt power supply
• Low power ISO-CMOS technologyApplications
• Synchronization and timing control for T1 and CEPT digital trunk transmission links
• ST- BUS clock and frame pulse source