MT4LC4M4E9中文资料美光数据手册PDF规格书

GENERAL DESCRIPTION

The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are “don’t care”). READ and WRITE cycles are selected with the WE# input.

FEATURES

• Industry-standard x4 pinout, timing, functions and packages

• State-of-the-art, high-performance, low-power CMOS silicon-gate process

• Single power supply (+3.3V ±0.3V or +5V ±10)

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-BEFORE-RAS# (CBR)

• Optional Self Refresh (S) for low-power data retention

• 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh)

• Extended Data-Out (EDO) PAGE MODE access cycle

• 5V-tolerant inputs and I/Os on 3.3V devices