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MT48LC16M8A2FC-8ELIT中文资料镁光数据手册PDF规格书
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MT48LC16M8A2FC-8ELIT规格书详情
General Description
The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.
The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• Auto refresh mode; standard and low power
– 64ms, 4096-cycle (industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• AEC-Q100
• PPAP submission
• 8D response time
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
Micron |
2022+ |
原厂原包装 |
8600 |
全新原装 支持表配单 中国著名电子元器件独立分销 |
询价 | ||
Micron Technology Inc |
23+/24+ |
54-TSOP |
8600 |
只供原装进口公司现货+可订货 |
询价 | ||
Micron |
2018+ |
TSOP54 |
50000 |
专营Micron全线品牌假一赔万原装进口货可开增值税发票 |
询价 | ||
MICRON |
23+ |
NA |
312 |
专做原装正品,假一罚百! |
询价 | ||
Micron Technology Inc. |
21+ |
54-TSOP II |
56200 |
一级代理/放心采购 |
询价 | ||
micron(镁光) |
23+ |
N/A |
589610 |
新到现货 原厂一手货源 价格秒杀代理! |
询价 | ||
MICRON |
2405+ |
原厂封装 |
12500 |
15年芯片行业经验/只供原装正品:0755-83267371邹小姐 |
询价 | ||
MICRON |
19+ |
TSSOP-54 |
256800 |
原厂代理渠道,每一颗芯片都可追溯原厂; |
询价 | ||
Micron |
22+ |
54TSOP II |
9000 |
原厂渠道,现货配单 |
询价 | ||
Micron |
23+ |
54TSOP II |
8000 |
只做原装现货 |
询价 |