SYNCHRONOUS DRAM

SYNCHRONOUS DRAM MT48LC16M4A2 – 4 Meg x 4 x 4 banks MT48LC8M8A2 – 2 Meg x 8 x 4 banks MT48LC4M16A2 – 1 Meg x 16 x 4 banks FEATURES • PC66-, PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined oper

文件：1.45885 Mbytes 页数：55 Pages

MICRON

美光

SYNCHRONOUS DRAM

文件：2.18875 Mbytes 页数：55 Pages

MICRON

美光

SYNCHRONOUS DRAM

Micron

美光

SYNCHRONOUS DRAM

SYNCHRONOUS DRAM MT48LC16M4A2 – 4 Meg x 4 x 4 banks MT48LC8M8A2 – 2 Meg x 8 x 4 banks MT48LC4M16A2 – 1 Meg x 16 x 4 banks FEATURES • PC66-, PC100-, and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined oper

文件：1.45885 Mbytes 页数：55 Pages

MICRON

美光

SYNCHRONOUS DRAM

文件：2.18875 Mbytes 页数：55 Pages

MICRON

美光

SYNCHRONOUS DRAM

文件：2.18875 Mbytes 页数：55 Pages

MICRON

美光

64Mb: x4, x8, x16 SDRAM

SYNCHRONOUS DRAMMT48LC16M4A2  – 4 Meg x 4 x 4 banks\nMT48LC8M8A2  – 2 Meg x 8 x 4 banks\nMT48LC4M16A2  – 1 Meg x 16 x 4 banksFEATURES\n• PC66-, PC100-, and PC133-compliant\n• Fully synchronous; all signals registered on positive edge of system clock\n• Internal pipelined operation; column address ca • PC66-, PC100-, and PC133-compliant\n• Fully synchronous; all signals registered on positive edge of system clock\n• Internal pipelined operation; column address can be changed every clock cycle\n• Internal banks for hiding row access/precharge\n• Programmable burst lengths: 1, 2, 4, 8, or full pag;

Micron

美光

Package：54-TSOP（0.400"，10.16mm 宽）；包装：托盘 类别：集成电路（IC） 存储器 描述：IC DRAM 64MBIT PAR 54TSOP II

Micron Technology Inc.

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR）剪切带（CT） 类别：集成电路（IC） 存储器 描述：IC SDRAM 64MBIT 133MHZ 54TSOP

Micron Technology Inc.

Package：54-TSOP（0.400"，10.16mm 宽）；包装：托盘 类别：集成电路（IC） 存储器 描述：IC DRAM 64MBIT PAR 54TSOP II

Micron Technology Inc.