SYNCHRONOUS DRAM

General Description The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728

文件：1.82868 Mbytes 页数：55 Pages

MICRON

美光

512Mb x4, x8, x16 SDRAM

文件：2.50339 Mbytes 页数：68 Pages

MICRON

美光

SYNCHRONOUS DRAM

GENERAL DESCRIPTION\nThe 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-b • PC100- and PC133-compliant\n• Fully synchronous; all signals registered on positive\n   edge of system clock\n• Internal pipelined operation; column address can be\n   changed every clock cycle\n• Internal banks for hiding row access/precharge\n• Programmable burst lengths: 1, 2, 4, 8, or full pag;

Micron

美光

SYNCHRONOUS DRAM

General Description The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728

文件：1.82868 Mbytes 页数：55 Pages

MICRON

美光

512Mb x4, x8, x16 SDRAM

文件：2.50339 Mbytes 页数：68 Pages

MICRON

美光

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

Micron Technology Inc.

Package：54-TSOP（0.400"，10.16mm 宽）；包装：卷带（TR）剪切带（CT） 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

Micron Technology Inc.

Package：54-TSOP（0.400"，10.16mm 宽）；包装：托盘 类别：集成电路（IC） 存储器 描述：IC DRAM 512MBIT PAR 54TSOP II

Micron Technology Inc.