MRC6011数据手册恩XP中文资料规格书

描述 Description

Overview Ushering in a new era in signal processing, the 24 Giga MACS MRC6011 is Our first Reconfigurable Compute Fabric (RCF) device. Ideally suited for MIPS-intensive, repetitive tasks, the MRC6011 offers a resource-efficient solution for computationally intensive applications, such as baseband processing for 2.5G and 3G basestations, broadband wireless access systems, and signal processing for advanced features such as Adaptive Antenna (AA) and Multi-User Detection (MUD). The highly programmable MRC6011 device offers system-level flexibility and scalability of a programmable DSP while zeroing in on the cost, power consumption, and processing capability of a traditional ASIC-based approach.
Key benefits of the RCF solution include:
Up to 21.6 Giga 16-bit MACS of processing power at 225 MHz
Up to 43.2 Giga 4-bit complex correlations per second at 225 MHz

特性 Features

RCF Core-Level


•RC Controller


•Optimized RISC processor for efficient C code compilation


•Instruction and data cache


•Support for hardware and software breakpoints


•Four programmable timers


•Eight external general-purpose output lines





•RC Array


•16 reconfigurable processing units


•16-bit data path


•Pipelined MAC unit





•Peripherals


•Two-channel Input Buffer


•Large Frame Buffer with eight Address Generation Units (AGUs)


•Special-purpose complex correlation unit supports spreading, complex scrambling, and complex correlation on 8-bit and 4-bit samples


•Single and burst transfer DMA controller


•Hardware reset for all RCF Cores






Module-Level


•RCF Cores


•Three identical RCF Cores per module, each with a powerful 16-element processing array


•Each RCF Core has a unique software-accessible ID register





•Bus Interconnects


•Multiplexed data input bus for dedicated high bandwidth input


•Multiplexed data routing directs input data to input buffer of target RCF Cores


•Separate DMA and controller bus





•Input Broadcast Routing Block


•Directs block interleaved Multiplexed Data Input (MDI) data to the appropriate RCF Cores






Device-Level


•RCF Core Modules


•Two identical and scalable RC modules (Module 0 and 1)





•Off-Chip Interface Feeds


•Two multiplexed data input bus interfaces


•Two Slave I/O bus interfaces





•DSP Host-Visible Memory


•Host-visible memory for traffic sharing between modules and for control code





•Module Shared memory


•Inter-module DMA-based data sharing





•Interrupt Controller


•6 interrupt request input lines


•8 Interrupt request outputs





•System Integration


•A single hardware reset signal can reset all RCF Cores and peripherals


•Single Clock Input for all RCF Cores


•JTAG port support for hardware and software debugging of individual cores





•Technology


•0.13 m process technology





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