MPC96877集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

Recommended Applications

• DDR II Memory Modules

• Zero Delay Board fan-out

特性 Features

• 1.8 V Phase Lock Loop Clock Driver for (DDR II) Applications

• Spread Spectrum Clock Compatible

• Operating Frequency: 100 MHz to 340 MHz

• 1 to 10 differential clock distribution (SSTL_18)

• 52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF (QFN)

• 52-lead Pb-free Package Available

• External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs

to the Input Clocks

• Single-Ended Input and Single-Ended Output Modes

• Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300

• Auto Power Down detect logic

Switching Characteristics

• Cycle-to-Cycle Jitter (>165 Mhz): 40 ps max.

• Output-to-Output Skew: 40 ps max.