MPC9608中文资料1:10 LVCMOS Zero Dela 1:10 LVCMOS Zero Delay Clock Buffer数据手册Renesas规格书

描述 Description

The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs.

特性 Features

1:10 outputs LVCMOS zero-delay buffer
Single 3.3 V supply
Supports a clock I/O frequency range of 12.5 to 200 MHz
Selectable divide-by-two for one output bank
Synchronous output enable control (CLK_STOP)
Output tristate control (output high impedance)
PLL bypass mode for low frequency system test purpose
Supports networking, telecommunications and computer applications
Supports a variety of microprocessors and controllers
Compatible to PowerQuicc I and II
Ambient Temperature Range -40°C to +85°C
32-lead Pb-free Package Available