MPC9352中文资料1:11 LVCMOS Zero Delay Buffer数据手册Renesas规格书

描述 Description

The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews lower than 200 ps, the device meets the needs of most demanding clock applications.

特性 Features

Configurable 11 Outputs LVCMOS PLL Clock Generator
Fully Integrated PLL
Wide Range of Output Clock Frequency of 16.67 MHz to 200 MHz
Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3 ÷ 2, 2 ÷ 3,
1 ÷ 3 and 1 ÷ 2
2.5 V and 3.3 V LVCMOS Compatible
Maximum Output Skew of 200 ps
Supports Zero-Delay Applications
Designed for High-Performance Telecom, Networking and Computing
Applications
32-Lead LQFP Package
32-Lead Pb-Free Package Available
Ambient Temperature Range –40°C to +85°C