PowerQUICC 32-Bit Power Arch SoC, 2 X 1.2GHz, DDR2/3, PCIe, GbE, SRIO, SEC, 0 to 105C, R2.2.1

NXP’s next-generation PowerQUICC® III integrated communications processors are designed to provide solutions for symmetrical and asymmetrical multi-core systems. Based on the scalable e500 processor and system-on-chip (SoC) platform, they deliver dual-core gigahertz plus processing performance with • Dual e500 Power Architecture cores scaling to 1.5 GHz\n• 1 MB L2 cache/SRAM with I/O stashing\n• 32 KB I/D L1 cache per core\n• Dual integrated DDR2/DDR3 SDRAM memory controllers • 64-bits (72-bits with ECC) per controller\n• to 800 MHz datarate\n• Four integrated Ethernet controllers (enhanced TS;

恩XP

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications

文件：1.41236 Mbytes 页数：140 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications

文件：1.41236 Mbytes 页数：140 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications

文件：1.41236 Mbytes 页数：140 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体