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MPC8541CPXAJD规格书详情
The MPC8541E integrates a PowerPC™ processor core built on Power Architecture™ technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8541E is a member of the PowerQUICC™ III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual.
Overview
The following section provides a high-level overview of the MPC8541E features. Figure 1 shows the major functional units within the MPC8541E.
Key Features
The following lists an overview of the MPC8541E feature set.
• Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
• Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
— Data Encryption Standard Execution Unit (DEU)
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced Encryption Standard Unit (AESU)
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
— ARC Four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message Digest Execution Unit (MDEU)
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
• High-performance RISC CPM
— Two full-duplex fast communications controllers (FCCs) that support the following protocol:
– IEEE Std 802.3™/Fast Ethernet (10/100)
— Serial peripheral interface (SPI) support for master or slave
— I2C bus controller
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
• 256 Kbytes of on-chip memory
— Can act as a 256-Kbyte level-2 cache
— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
— Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— SRAM operation supports relocation and is byte-accessible
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing).
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
– Individual line locks set and cleared through Book E instructions or by externally mastered transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses (Continue....)
产品属性
- 型号:
MPC8541CPXAJD
- 功能描述:
微处理器 - MPU PQ 37 LITE 8555
- RoHS:
否
- 制造商:
Atmel
- 处理器系列:
SAMA5D31
- 核心:
ARM Cortex A5
- 数据总线宽度:
32 bit
- 最大时钟频率:
536 MHz
- 程序存储器大小:
32 KB 数据 RAM
- 大小:
128 KB
- 接口类型:
CAN, Ethernet, LIN, SPI,TWI, UART, USB
- 工作电源电压:
1.8 V to 3.3 V
- 最大工作温度:
+ 85 C
- 安装风格:
SMD/SMT
- 封装/箱体:
FBGA-324
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
FREESCAL |
23+ |
BGA |
19726 |
询价 | |||
FREESCALE |
22+ |
FCPBGA78329S |
2000 |
原装现货库存.价格优势 |
询价 | ||
FREESCALE |
23+ |
BGA |
90000 |
只做原厂渠道价格优势可提供技术支持 |
询价 | ||
FREESCA |
2020+ |
BGA |
80000 |
只做自己库存,全新原装进口正品假一赔百,可开13%增 |
询价 | ||
FREESCALE |
23+ |
微处理器 |
28500 |
授权代理直销,原厂原装现货,假一罚十,特价销售 |
询价 | ||
FREESCALE |
2021+ |
BGA |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 | ||
NXP |
22+ |
783FCPBGA |
9000 |
原厂渠道,现货配单 |
询价 | ||
NXP |
23+ |
783FCPBGA |
4568 |
原厂原装正品现货,代理渠道,支持订货!!! |
询价 | ||
Freescale Semiconductor - NXP |
23+ |
783-BBGA |
11200 |
主营:汽车电子,停产物料,军工IC |
询价 | ||
FREESCALE |
21+ |
BGA |
1000 |
诚信至上只做原装 |
询价 |