PQ37 8540-PbFr r2.1

Addressing the needs for higher compute density and lower system cost, Our MPC8540 integrated host processor is designed to provide the highest level of performance and integration available today. The MPC8540 is Our first device utilizing the e500 core, is the industry's first RapidIO®-enabled proc • Embedded e500 compatible core available from 600 MHz up to 1 GHz\n • 32-bit, dual-issue, superscalar, seven-stage pipeline\n • 1850 MIPS at 800 MHz (est. Dhrystone 2.1)\n • 32 KB L1 data and 32 KB L1 instruction cache with line locking support\n • 256 KB on-chip L2 cache with direct mapped capabil;

恩XP

PQ37 8540-PbFr r2.1

Addressing the needs for higher compute density and lower system cost, Our MPC8540 integrated host processor is designed to provide the highest level of performance and integration available today. The MPC8540 is Our first device utilizing the e500 core, is the industry's first RapidIO®-enabled proc • Embedded e500 compatible core available from 600 MHz up to 1 GHz\n • 32-bit, dual-issue, superscalar, seven-stage pipeline\n • 1850 MIPS at 800 MHz (est. Dhrystone 2.1)\n • 32 KB L1 data and 32 KB L1 instruction cache with line locking support\n • 256 KB on-chip L2 cache with direct mapped capabil;

恩XP

PQ37 8540-PbFr r2.1

Addressing the needs for higher compute density and lower system cost, Our MPC8540 integrated host processor is designed to provide the highest level of performance and integration available today. The MPC8540 is Our first device utilizing the e500 core, is the industry's first RapidIO®-enabled proc • Embedded e500 compatible core available from 600 MHz up to 1 GHz\n • 32-bit, dual-issue, superscalar, seven-stage pipeline\n • 1850 MIPS at 800 MHz (est. Dhrystone 2.1)\n • 32 KB L1 data and 32 KB L1 instruction cache with line locking support\n • 256 KB on-chip L2 cache with direct mapped capabil;

恩XP