MPC852TZT50

Hardware Specifications

MPC852TZT50A

PowerQUICC, 32 Bit Power Architecture, 50MHz, Communications Processor, 0 to 95C; Maximum frequency operation of the MPC8xx core is 100 MHz\n• Maximum frequency operation of the external bus is 66 MHz in 1:1 mode\n• Single-issue, 32-bit core (compatible with Power Architecture technology)with 32, 32-bit general-purpose registers (GPRs)\n• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)\n• 32 address lines\n• Memory controller (eight banks)\n• General-purpose timers\n• System integration unit (SIU)\n• Interrupts\n• Communications processor module (CPM)\n• Two baud rate generators\n• Two SCCs (serial communication controllers) (10BaseT Ethernet, HDLC, Transparent)\n• One SMC (serial management channel)\n• One SPI (serial peripheral interface)\n• Fast Ethernet controller (FEC)\n• PCMCIA interface\n• Debug interface\n• 1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility\n• 256-pin, 23*23 1.27 ball pitch (BGA) package\n;

The MPC852T PowerQUICC® processor delivers a versatile, integrated solution for controller applications such as communications and networking products.\nOffers ideal support for ethernet to ethernet applications such as line card\nProvides superior performance over traditional architectures by offloading communications intensive processing from the embedded core\nIncludes strong third-party tools support through NXP®.s Design Alliance Program\n